Many modern electronic systems have memory architecture that may comprise physical memory and logical memory. For example, when addressing memory, a processor may reference a memory address, which may result in a cache hit if the memory address is associated with a cache. However, a miss can result in delay while the data associated with the memory address is fetched from another memory device, such as another level of cache, main memory, or a mass storage device.
Other memory architectures may use translation of addresses in order to access physical memory devices. For example, a processor may request data access using a virtual address that may need to be translated to a physical address. The virtual address may then be translated to a physical address before the physical memory can be accessed.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.